USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
- USB 3.2
- TSMC
- 16nm
- FFC
- In Production
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
USB 3.0 PHY IP, Silicon Proven in TSMC 7FF
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
All USB 3.2 Gen2X1 host and peripheral applications are supported up to 10Gbps by the USB 3.2 Gen2X1 transceiver IP.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF
The USB 3.2 Gen2X1 transceiver IP offers all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The logic required to create and validate designs for diverse applications is provided by HDMI Transmitter (TX) IP solutions, whi…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+
For Gigabit 10/100/1000 Ethernet applications, the GPHY is a integrated single chip.
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 28SF
The JESD204B Tx-Rx PHY IP interface, which offers full support for the JESD204B synchronous and serial data interface, is aligned…
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
The PCIe 2.0 transceiver IP supports all PCIe 2.0 Base applications.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 40ULP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
A comprehensive selection of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
High-bandwidth applications can avail advantage of PCIe 3.0 PHY IP's high performance, multi-lane scalability, and low-power layo…
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
For the high-bandwidth applications, PCIe 3.0 PHY IP offers high-performance, multi-lane capabilities, and low-power design.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design.
PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design.
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consu…