The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Spe…
ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips.
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…
The Serial Low-Power Inter-chip Media bus protocol (SLIMbus®) software stack provides developers a method for easy development, i…
MIPI SLIMbus Hardware Validation Platform
The SLIMbus® (Serial Low-power Inter-chip Media bus protocol) Hardware Validation Platform provides the mobile industry a versati…
The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose con…
The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an…
Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers.
Mobile radio communication systems are complex multi-radio systems comprising several transceivers.
MIPI M-PHY® 3.1 Analog Transceiver
MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
The MIPI® D-PHY is compliant to the MIPI D-PHY Specification v2.1.
MIPI D-PHY Analog Transceiver IP Core
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI®) Alliance was created to d…
Combination MIPI CPHY-DPHY Analog Interface
The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
MIPI CPHY v1.1 Analog Interface
The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…
The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communicat…
The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile appl…
The DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobi…