The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v.
- USB
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v.
USB 3.0 Device Upgrade IP Core
The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power …
The USB 3.0 Device IP core enables designers in the PC, mobile, consumer and communication markets to bring significant power and…
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s…
The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
High Speed Inter-CHIP USB 2.0 PHY
USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications.
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Spe…
ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
The Open NAND Flash Interface (ONFI) is an Open standard for NAND Flash Memory chips.
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…
The Serial Low-Power Inter-chip Media bus protocol (SLIMbus®) software stack provides developers a method for easy development, i…
MIPI SLIMbus Hardware Validation Platform
The SLIMbus® (Serial Low-power Inter-chip Media bus protocol) Hardware Validation Platform provides the mobile industry a versati…
The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose con…
The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an…
Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers.
Mobile radio communication systems are complex multi-radio systems comprising several transceivers.
MIPI M-PHY® 3.1 Analog Transceiver
MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…