USB 2.0 Host IP Core

The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface. The USB 2.0 Host IP supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.

The IP consists of an Enhanced Host Controller Interface (EHCI) and a companion Open Host Controller Interface (OHCI). The EHCI processor handles HS transactions and is the default owner of the root hub that connects to the downstream ports. In a downstream data transfer, the EHCI sends data to the Host Parallel Interface Engine (HPIE) for encoding and CRC appending. Data received by the USB 2.0 Root Hub is forwarded to the downstream ports. Similarly, FS and LS transactions are handled by the OHCI, Host Serial Interface Engine (HSIE), and USB 1.1 Root Hub. The Root Hub performs multiplexing and forwarding of packets between the downstream ports and USB 2.0/1.1 Root Hubs. Up to 8 downstream ports can be connected to the USB 2.0 Host IP core. With the addition of optional ULPI Wrappers, the Arasan USB 2.0 Host IP core can be connected directly to a 16-bit standard UTMI or 8-bit ULPI transceiver.

Arasan is the among the industry’s first providers of USB IP with the launch of its USB 1.1 Device IP in 1996 and the industries ONLY provider to offer a Total USB 2.0 IP Solution which includes its USB 2.0 Host IP Core, USB 2.0 Device IP Core, USB 2.0 Hub IP, USB 2.0 OTG IP, the USB 2.0 PHY IP and software for multiple OS.

Compliance

• USB specification revision 2.0
• EHCI specification revision 1.0

USB 2.0 Host

• Supports up to 127 devices and 8 downstream ports
• OHCI companion processor for USB 1.1 transfers
• 16-bit UTMI and 8-bit ULPI interfaces
• Direct addressing all IP core registers from AHB, PCI, or custom bus
• DMA controller supports high-speed data transfers between USB Host IP and host bus

Host Interface

• 8, 16, or 32-bit host bus
• Optional 133 MHz AHB Rev. 2.0 master/slave interface
• Optional 33 MHz PCI Rev. 2.2 master/target interface
• Optional custom bus interface

• Fully compliant to USB 2.0 specifications
• Highly flexible and configurable
• Ideal for easy and cost-effective device integration
• Premier direct support from Arasan IP Engineering Team

• RMM-compliant synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents
• Simulation scripts