PCIe End Point IP Core

The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.

The highly configurable PCIe Endpoint IP core supports x1, x2, and x4 lane with a selection of 32/64-bit data path. Depending on design requirements, a maximum of 8 VCs and 8 TCs are supported. The IP core consists of many useful features that can be included to enhance system performance and to address special design needs in different applications. The data link layer allows the configuration of infinite credits to boost the flow control efficiency. By-pass mode, cut-through mode, and store-and-forward mode are other optional items. The transport layer features include configurable ECRC generation and checking, support for up to 64 configurable outstanding non-posted requests, and configurable payload size from 128 to 4 Kbytes.

The Arasan PCI Express End Point IP has an 8/16-bit PIPE compliant physical layer interface that can be connected directly to any standard PHY such as the Philips PX1011A, PX1012A, or similar PHY devices. The Arasan PCIe End Point IP core together with the PHY provides a flexible PCI Express endpoint solution with additional features such as polarity inversion, lane reversal, beacon, and wake-up mechanisms, link training LTSSM, and link speed negotiation.

Multi-functions are supported by the inclusion of the function control blocks with their registers and FIFOs. Additional features include hot-plug and hot-swap capability, legacy PCI, MSI, and MSI-X interrupts, ASPM and software-controlled power management, advance error reporting, power budget capability, etc.

• Compliance with PCI Express Specification Rev 1.1 and Rev2.0 and PIPE Specification Rev 1.87
• Transaction Layer Supports by-pass, cut-through, and store-and-forward modes
• Infinite credits configurable for any queue
• Supports up to 8 VCs and 8 TCs
• Supports multi-function
• ECRC generation and checking
• TC/VC mapping
• VC capability structure support
• Flow control initialization
• TLP retry on errors
• Data Link Layer
• Retry buffer size
• Payload size from 128 to 4 Kbytes
• Read request size
• LCRC for TLP and DLLP
• Physical Layer
• 8-bit/16-bit PIPE interface
• x1, x2, and x4 lanes
• Polarity inversion
• Lane reversal
• Link speed negotiation
• Beacon and wake-up mechanisms
• Data scrambling and de-scrambling
• Insertion/deletion of SKIP ordered sets
• ASPM and software controlled power management
• Legacy PCI, and MSI/MSI-X interrupts support
• Optional advanced error reporting
• 32-bit, or 64-bit data path
• 125 MHz or 250 MHz core frequency support up to 32 configurable outstanding non-posted requests
• Supports all required inband messages
• Low transmit and receive latency
• Up to 6 configurable BAR with 32-bit or 64

• Fully compliant core
• Premier direct support from Arasan IP core designers
• Easy-to-use industry standard test environment
• Unencrypted source code allows easy implementation
• Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass

• RMM Compliant Synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents