TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
- TSMC
- 5nm
- N5FF
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
Ultra Ethernet Verification IP
The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet …
The AVSBus Verification IP provides an effective and efficient way to verify the components interfacing with AVSBus interface of …
Comprehensive MAC-to-PCS Protocol Validation Solution The 100G Ethernet Verification IP (VIP) offers a robust and high-performanc…
The INTERLAKEN Verification IP Product is the comprehensive INTERLAKEN interface protocol validation solution.
CXL 4.0/3.2/3/2 Verification IP
The CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or…
ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connecti…
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
Accelerated confidence in simulation-based verification of RTL designs with Ethernet networking interfaces Avery TSN Ethernet Ver…
Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7 Av…
USB 2.0 Mass Storage Devices Design Platform
The USB 2.0 Mass Storage Design Platform is a , integrated solution, dedicated to a wide range of USB-based Mass Storage Devices.
The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v.
USB 3.0 Device Upgrade IP Core
The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power …
The USB 3.0 Device IP core enables designers in the PC, mobile, consumer and communication markets to bring significant power and…
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s…
The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
High Speed Inter-CHIP USB 2.0 PHY
USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications.