Empowering customers to thrive in the AI Era, INNOSILICON™ introduces its most 112G SerDes (Serializer/Deserializer) and Controll…
- Multi-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Empowering customers to thrive in the AI Era, INNOSILICON™ introduces its most 112G SerDes (Serializer/Deserializer) and Controll…
Fully compliant with ISO/IEC 7816 Specifications Supports IEC 7816-3 Device/Card functionality.
The ISO/IEC 14443 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs t…
The PMBus Verification IP provides an effective and efficient way to verify the components interfacing with PMBus interface of an…
The CAN XL Verification IP provides an effective & efficient way to verify the CAN components of an IP or SoC.
Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification The UA Link PCS IP…
AMBA AHB 3 Lite Verification IP
The AMBA 3 AHB-Lite Verification IP provides an effective & efficient way to verify the components interfacing with AMBA®3 AHB-Li…
The AMBA AXI3 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA® AXI3 bus of a…
KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physica…
KMX 40G MAC and PCS core, which including media access control (MAC) module, physical coding sublayer (PCS) module and physical m…
100G UDP/IP Hardware Protocol Stack Core
The core Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connect…
TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
Ultra Ethernet Verification IP
The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet …
Comprehensive MAC-to-PCS Protocol Validation Solution The 100G Ethernet Verification IP (VIP) offers a robust and high-performanc…
The INTERLAKEN Verification IP Product is the comprehensive INTERLAKEN interface protocol validation solution.
ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connecti…
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
Accelerated confidence in simulation-based verification of RTL designs with Ethernet networking interfaces Avery TSN Ethernet Ver…
Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7 Av…
USB 2.0 Mass Storage Devices Design Platform
The USB 2.0 Mass Storage Design Platform is a , integrated solution, dedicated to a wide range of USB-based Mass Storage Devices.