USB 2.0 Hub IP Core
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s…
Overview
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode. The USB 2.0 Hub IP core consists of the Hub Controller, Hub Repeater, Transaction Translators, Routing Logic, and Downstream Ports.
The USB 2.0 Hub Controller controls the operation of the USB hub by interpreting both the USB commands and Hub class-specific commands. High-speed packets originating from the root hub are forwarded by the Hub Repeater to the HS Downstream Ports through the Routing Logic. Full-speed and low-speed packets scheduled by the host system software as split transactions are forwarded to the Transaction Translators. The Transaction Translators handle split transactions that convey isochronous, interrupt, control, and bulk transfers across the high-speed bus to and from the full-speed and low-speed devices attached to the hub. The Transaction Translators also perform CRC on incoming packets from the Hub Repeater or Routing Logic. The Routing Logic connects the Hub Repeater to the Downstream Ports in a high-speed transfer, and it connects the Transaction Translators to the Downstream Ports in a full-speed or low-speed transfer. The number of Downstream Ports is scalable.
The Arasan Auto-configure and Auto-wire are pre-compiled C language utilities that allow users to have the freedom to fully customize their designs.
Arasan is the among the industry’s first providers of USB IP with the launch of its USB 1.1 Device IP in 1996 and the industries ONLY provider to offer a Total USB 2.0 IP Solution which includes its USB 2.0 Host IP Core, USB 2.0 Device IP Core, USB 2.0 Hub IP, USB 2.0 OTG IP, the USB 2.0 PHY IP and software for multiple OS.
Key features
- High speed support: 480 Mbit/s
- Full speed support: 12 Mbit/s
- USB 2.0 Compliant
- High/Full speed support using 8/16 bit UTMI/ULPI interface
- Optional PIO Mode for each endpoint (can be used for Interrupt endoints)
- System bus Master/Target clock
- UTMI Interface Clock: 30/60 MHz
- Endpoint Configuration
- Configurable up to 15 downstream ports
- Configuration options: Bulk, control, isochronous, interrupt
- Dedicated control endpoint zero
- Configurable dual port RAM shared between endpoints
- USB Suspend/Resume support
- LPM Support
Block Diagram
Benefits
- Fully compliant to USB 2.0 specifications
- Highly flexible and configurable
- Ideal for easy and cost-effective device integration
- Premier direct support from Arasan IP Engineering Team
What’s Included?
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
- Simulation scripts
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about USB IP core
Exploring USB Applications and the Impact of USB IP
Understanding USB IP and Its Role in SOC Integration
SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications
eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
Incorporating Quality into Reusable Interface IP
Frequently asked questions about USB IP cores
What is USB 2.0 Hub IP Core?
USB 2.0 Hub IP Core is a USB IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.