VESA introduced the first Display Stream Compression (DSC) standard in 2014.
- VESA DSC
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
SONET/SDH OC-3 Transceiver/CDR
The SMS2011 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
Lithe Layer 2 Gigabit Ethernet Switching IP
The Lithe Layer 2 Gigabit Ethernet Switching IP is a comprehensive solution for building scalable and efficient network infrastru…
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 The MIPI CSI-2 IP core is a scalab…
The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interfa…
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…
MIPI D-PHY1.2 CSI/DSI TX and RX
The MIPI D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimedia…
The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devi…
The USB4 Verification IP (MX_USB4_VIP) provides a capable verification solution for the USB4 protocol which incorporating bus fun…
The MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as p…
The vendor provides configurable JESD204B TX/RX verification IP.
The AMBA-AXI VIP provides a solution for verification of AMBA-AXI protocol version 2.0.
The AHB Verification IP provides a solution for Verification of AMBA 3.0 AHB-Lite protocol v1.0 component of a SOC or ASIC.
The RapidIO Verification IP (VIP) provides capable compliance verification solution for the RapidIO protocol.