Embrace the future of digital media with the VESA VDC-M v1.2 Encoder IP core.
- VESA DSC
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Embrace the future of digital media with the VESA VDC-M v1.2 Encoder IP core.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors.
MIPI M-PHY® 4.1 Analog Transceiver
MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
Host / device LIN controller IP
The LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications.
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…
Arasan Chip Systems is a System on Chip (SoC) Intellectual Property (IP) provider of a suite of Mobile Industry Processor Interfa…
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.
SONET/SDH OC-3 Transceiver/CDR
The SMS2011 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
Lithe Layer 2 Gigabit Ethernet Switching IP
The Lithe Layer 2 Gigabit Ethernet Switching IP is a comprehensive solution for building scalable and efficient network infrastru…
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 The MIPI CSI-2 IP core is a scalab…
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…