Vendor: Xilinx, Inc. Category: Ethernet

QSGMII

The Xilinx Ethernet Quad Serial Gigabit Media Independent Interface PCS/PMA or QSGMII IP LogiCORE™ IP provides an Ethernet Physic…

Overview

The Xilinx Ethernet Quad Serial Gigabit Media Independent Interface PCS/PMA or QSGMII IP LogiCORE™ IP provides an Ethernet Physical Coding Sublayer (PCS) with an aggregation of four 10/100/1000M ports to one five gigabit transceiver.  QSGMII interfaces are implemented using transceivers in Virtex®-7 or  Kintex™-7 devices.  On the front end, the LogiCORE IP can also interface seamlessly to four Ethernet MACs through a built-in Gigabit Media Independent Interface (GMII).  This IP is available through CORE Generator™ software at no charge to help you accelerate your time to market.  It is built upon our existing Serial Gigabit Media Independent Interface PCS/PMA IP.

Key features

  • Designed to Cisco’s proprietary QSGMII specification version 1.2
  • Implements 4 lanes of 10/100/1000 Mbps channels
  • IEEE 802.3-2008 Clause 36 implementation of PCS (Physical Coding Sublayer) for encapsulation, line encoding and link synchronization
  • Available at no charge in CORE Generator
  • Supports internal or external GMII for interfacing to a MAC or customer logic
  • Integrated with the Xilinx 7-series embedded transceivers
  • Available in VHDL or Verilog netlist simulation model

Specifications

Identity

Part Number
QSGMII
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Ethernet IP core

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Frequently asked questions about Ethernet IP cores

What is QSGMII?

QSGMII is a Ethernet IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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