Vendor: Xilinx, Inc. Category: Test / Debug

ChipScope Pro IBERT for Virtex-7 GTX

The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virt…

Overview

The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virtex-7 FPGA GTX transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers. Communication logic is also included to allow the design to be run-time accessible through Joint Test Action Group (JTAG). This core can be used as a self-contained or open design, based on customer configuration as described in this document.

Key features

  • Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
  • Provides a user-selectable number of Virtex-7 FPGA GTX transceivers
  • Transceivers can be customized for the desired line rate, reference clock rate, reference clock source,and data path width
  • Requires a system clock that can be sourced from a pin or one of the enabled GTX transceivers

Specifications

Identity

Part Number
ChipScope Pro IBERT for Virtex-7 GTX
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about SerDes Test / Debug IP cores

What is ChipScope Pro IBERT for Virtex-7 GTX?

ChipScope Pro IBERT for Virtex-7 GTX is a Test / Debug IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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