Vendor:
Rambus, Inc.
Category:
PCI Express
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
Overview
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
This includes the following features:
• Root Complex master requests are generated using simple test control scripts. A basic set of test cases is included with the suite to generate standard PCI Express transactions including configuration, data transfers, DMA and interrupts.
• Automatic response to DUT master requests including providing completion responses.
• Modeling of Root Complex memory regions. These memory regions are used store data being send to and received from the DUT. The data in these memory regions can be automatically checked to insure proper operation.
• Performs Root Complex physical and data-link layer functions including error detection and correction
• Logging and display of transaction layer traffic on the PCI Express bus in a user-friendly format.
The fast setup and operation of the PCIe Testbench makes it easy for users to quickly and comprehensively perform simulations of designs which include Rambus PCI Express cores.
The PCIe Testbench is not a PCI Express full compliance suite. RAMBUS recommends the use of the Avery Logic PCI-Xactor PCI Express Compliance Suite for ASIC validation.
The Testbench is compliant with PCI Express Base Specification Revision 3.0/2.0/ 1.1
Rambus also provides IP Core customization services. Contact Rambus for a quote.
This includes the following features:
• Root Complex master requests are generated using simple test control scripts. A basic set of test cases is included with the suite to generate standard PCI Express transactions including configuration, data transfers, DMA and interrupts.
• Automatic response to DUT master requests including providing completion responses.
• Modeling of Root Complex memory regions. These memory regions are used store data being send to and received from the DUT. The data in these memory regions can be automatically checked to insure proper operation.
• Performs Root Complex physical and data-link layer functions including error detection and correction
• Logging and display of transaction layer traffic on the PCI Express bus in a user-friendly format.
The fast setup and operation of the PCIe Testbench makes it easy for users to quickly and comprehensively perform simulations of designs which include Rambus PCI Express cores.
The PCIe Testbench is not a PCI Express full compliance suite. RAMBUS recommends the use of the Avery Logic PCI-Xactor PCI Express Compliance Suite for ASIC validation.
The Testbench is compliant with PCI Express Base Specification Revision 3.0/2.0/ 1.1
Rambus also provides IP Core customization services. Contact Rambus for a quote.
Key features
- Emulates a Root Complex device enabling simulation of a PCI Express design
- Test scripts are used to generate Root Complex master requests
- Automatically responds to DUT master requests
- Performs automatic data logging and checking
- Provided with a basic set of test cases
- Specifically designed for quick out -of-the-box setup and use
- Fast simulation speed
- PCI Express im Base Specification Revision 3.0/2.0/1.1 compliant
- Provided in source code form
Specifications
Identity
Part Number
PCIe Controller Testbench
Vendor
Rambus, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about PCIe IP cores
What is PCIe Controller Testbench?
PCIe Controller Testbench is a PCI Express IP core from Rambus, Inc. listed on Semi IP Hub.
How should engineers evaluate this PCI Express?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.