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Vendor:
Veriest Solutions Ltd.
Category:
SPI / QSPI XSPI
Flash SPI controller master/slave
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses.
Overview
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses. It supports SPI master mode with word lengths up to 32 bits. The APB interface connects seamlessly to the AMBA 3 APB Bus as an AMBA Bus slave. The Core is a fully synthesizable Verilog Model.
The IP performs serial to parallel and parallel to serial data conversions using a receive FIFO and a transmit FIFO as buffers. During compilation the depth of the receive FIFO, the depth of the transmit FIFO, and the FIFO widths can be configured, up to a maximum of 32 bits width x 32 lines depth.
The SPI Master Controller offers a mechanism for write and then read using the SPI bus. SPI RX words can be blocked if the specified number of words have already been transmitted by the SPI. TX word pops can be blocked until a gate is opened by the CPU. The SPI Master Controller supports all four combinations of SPI clock idle polarity and SPI clock data transfer phase configurations.
The SPI Master Controller supports one interrupt line. The interrupt can be configurable for the following conditions:
• Chip select assert or de-assert
• FIFOs overflow or underflow
• FIFOs pre-configured threshold interrupts
• Pre-configured SPI word and bit counters threshold
The IP performs serial to parallel and parallel to serial data conversions using a receive FIFO and a transmit FIFO as buffers. During compilation the depth of the receive FIFO, the depth of the transmit FIFO, and the FIFO widths can be configured, up to a maximum of 32 bits width x 32 lines depth.
The SPI Master Controller offers a mechanism for write and then read using the SPI bus. SPI RX words can be blocked if the specified number of words have already been transmitted by the SPI. TX word pops can be blocked until a gate is opened by the CPU. The SPI Master Controller supports all four combinations of SPI clock idle polarity and SPI clock data transfer phase configurations.
The SPI Master Controller supports one interrupt line. The interrupt can be configurable for the following conditions:
• Chip select assert or de-assert
• FIFOs overflow or underflow
• FIFOs pre-configured threshold interrupts
• Pre-configured SPI word and bit counters threshold
Key features
- Full-duplex operation allows simultaneous receive and transmit
- SPI Master mode operation
- APB Slave mode operation
- Four wire SPI bus – data rx, data tx, clock, chip select
- Memory mapped APB interface
- Buffered operation with separate configurable receive and transmit FIFOs
- Compliant with AMBA APB revision 3.0 specification
- Configurable SPI word width 8, 16, 24, 32 bits
- Optional PIF bus instead of APB bus.
- Supports up to 16 SPI slaves.
- Interrupts supports
What’s Included?
- Synthesizable Verilog RTL
- Verilog test bench and test cases
- Specman or System Verilog verification environment and test cases
- Detailed block diagram and technical documents
Specifications
Identity
Part Number
VV1100
Vendor
Veriest Solutions Ltd.
Type
Silicon IP
Provider
HQ:
Israel
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is Flash SPI controller master/slave?
Flash SPI controller master/slave is a SPI / QSPI XSPI IP core from Veriest Solutions Ltd. listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.