AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Test / Debug
ChipScope Pro IBERT for Kintex-7 GTX
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that…
Overview
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Kintex-7 FPGA GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers.
Key features
- Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core.
- Has user-selectable number of Kintex-7 FPGA GTX transceivers.
- Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width.
- Requires a system clock that can be sourced from a pin or one of the enabled GTX transceivers.
Specifications
Identity
Part Number
ChipScope Pro IBERT for Kintex-7 GTX
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Test / Debug IP core
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Frequently asked questions about SerDes Test / Debug IP cores
What is ChipScope Pro IBERT for Kintex-7 GTX?
ChipScope Pro IBERT for Kintex-7 GTX is a Test / Debug IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Test / Debug?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.