The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which…
- Protocol Bridge
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which…
Included at no additional charge with Vivado and ISE Design Suite.
The LogiCORE™ System Cache provides system level caching capability for AXI-4 based systems.
The AXI Protocol Checker core is designed to monitor AXI interfaces.
Included at no additional charge with EDK software.
The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN cont…
Mature solution featuring xHCI Host, Device, and Dual-Role
SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO
VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Interna…
PCI - AMBA AHB Device/Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices.
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices.
Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol.
Aliathon’s 100G add/drop multiplexor is targeted towards the next generation metro ring topologies for OTN.
MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applicat…
PCIe DMA Controller (Low Latency)
The RapidDMA IP solution offers a fully integrated, -configurable, multi-channel and low latency PCIe-DMA solution.
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver.
TSMC 55nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
HyperLink High Speed DSP Interface Core
The Integretek HyperLink Core allows the creation of a user defined system which can communicate with remote TI Cx66 DSP devices …
I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of d…
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can …