Vendor: Xilinx, Inc. Category: JESD204

JESD204

The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard.

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Overview

The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard.  The JESD204B specification describes serial data interface and the link protocol between data converters and logic devices.

This IP core supports line rates of up to 12.5 Gbps characterized to the JESD204B specification and line rates up to 16.1 Gbps not characterized to the JESD204B specification and between 1-32 lane configurations. The IP Core can be configured as JESD204 Transmitter for interfacing to DAC device or JESD204 Receiver for interfacing to ADC device. The JESD204 IP core is delivered as a netlist along with the supporting wrapper files.

Key features

  • Designed to JEDEC JESD204B specification
  • Supports scrambling and initial lane alignment
  • Supports 1-256 Octets per frame and 1-32 frames per multi-frame
  • Supports 1 to 32 lane configurations
  • Supports line rates up to 12.5 Gbps certified to the JESD204B spec
  • Supports line rates up to 16.1 Gpbs not certified to the JESD204B spec
  • Provides Physical and Data link layer functions
  • AXI4-Stream interface for data
  • AXI4-Lite for configuration interface

Specifications

Identity

Part Number
EF-DI-JESD204-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204?

JESD204 is a JESD204 IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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