LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support For the Serial RapidIO Gen 2 Xi…
- RapidIO
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support For the Serial RapidIO Gen 2 Xi…
Virtex-6 FPGA GTX Transceiver Wizard
The LogiCORE™ Virtex®-6 GTXTransceiver Wizard automates the task of creating HDL wrappers to configure the on-chip GTX transceive…
Virtex-6 FPGA GTH Transceiver Wizard
The LogiCORE™ IP Virtex®-6 GTH Transceiver Wizard automates the task of creating HDL wrappers to configure Xilinx Virtex-6 FPGA G…
Virtex-5 FPGA RocketIO GTX Transceiver Wizard
The LogiCORE™ IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard automates the task of creating HDL wrappers to configure the Xilin…
Virtex-5 FPGA RocketIO GTP Transceiver Wizard
The LogiCORE™ IP Virtex-5 FPGA RocketIO GTP Transceiver Wizard automates the task of creating HDL wrappers to configure Xilinx Vi…
Virtex-4 FX FPGA RocketIO Multi-Gigabit Transceiver Wizard
LogiCORE™ IP High-Speed Serial Transceiver Wizards automate the task of creating HDL wrappers to configure Xilinx FPGA on-chip tr…
Triple-Rate SDI on Spartan-6 FPGAs
The Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital …
Spartan-6 FPGA GTP Transceiver Wizard
The LogiCORE™ IP Spartan-6 GTP Transceiver Wizard automates the task of creating HDL wrappers to configure the on-chip GTP transc…
The Xilinx Ethernet Quad Serial Gigabit Media Independent Interface PCS/PMA or QSGMII IP LogiCORE™ IP provides an Ethernet Physic…
The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard.
Zynq Bus Functional Model (BFM)
The ability to purchase Zynq BFM has been discontinued as of December 1, 2016.
ChipScope Pro IBERT for Virtex-7 GTX
The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virt…
ChipScope Pro IBERT for Kintex-7 GTX
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that…
The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or …
The AMBA® ( Microcontroller Bus Architecture) AHB-Lite ( High Performance Bus) to AXI ( extensible interface) bridge translates A…
7 Series FPGA Transceivers Wizard
The LogiCORE™ IP 7 Series FPGAs Transceivers Wizard automates the task of creating HDL wrappers to configure Xilinx 7 Series FPGA…
The Dual HDLC controller provides two full-duplex HDLC channels, each with 512-byte data FIFO buffers for both directions.
UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
Flash SPI controller master/slave
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses.