Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
Compliant with USB2.0 and USB1.1 specification
Full compatible with PIPE4.2 interface specification
SLM High-Speed Access & Test IP
Leverage existing functional interfaces to access DFT or SLM network over entire silicon lifecycle The SLM High-Speed Access and …
Quad Serial Gigabit Media Independent Interface (QSGMII)
QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate…
Universal Serial 10GE Media Independent Interface (USXGMII)
The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
Serial Gigabit Media Independent Interface (SGMII)
SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MA…
High performance Ethernet PCS IP core for data centers, hyperscaler and AI applications The 800G Ethernet PCS IP core is a silico…
The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself …
A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …
USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
SATA/SAS 3.0 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …
With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…
High-speed LVDS (Low-Voltage Differential Signaling) transceiver
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint.
Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).