Vendor: Comcores Category: Single-Protocol PHY

Quad Serial Gigabit Media Independent Interface (QSGMII)

QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate…

Overview

QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps. It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.

The IP is compliant with IEEE 802.3, SGMII, QSGMII (as defined by Broadcom) and is targeting ASIC’s and has gone through full UVM verification and is silicon proven.

Key features

Delivering Performance

  • Aggregates 4 independent Gigabit Ethernet ports into a single serial link
  • Operates at 5.0 Gbps using 8b/10b encoding
  • Full duplex support for all 4 ports
  • Supports auto-negotiation and link training
  • Compatible with standard MAC/PHY interfaces
  • Built-in synchronization and alignment logic

Applications

  • Multi-port Gigabit Ethernet Switches
  •  Automotive Ethernet Aggregation
  •  Industrial Networking
  •  Access Network Equipment (OLT, ONU)

Block Diagram

Quad Serial Gigabit Media Independent Interface (QSGMII) block diagram

What’s Included?

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • IP in Source code or encrypted RTL
  • Comprehensive documentation, including User Manual, Release Note and Product Brief
  • Simulation Environment, including basic test environment, test cases and test scripts
  • Access to a support system and direct support from Comcores Engineers

Specifications

Identity

Part Number
Quad Serial Gigabit Media Independent Interface (QSGMII)
Vendor
Comcores
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Comcores
HQ: Denmark

Learn more about Single-Protocol PHY IP core

How Time Sensitive Networking powers the Software Defined Vehicle

Software-Defined Vehicles (SDVs) are turning cars into distributed real-time computing platforms. Instead of dozens of standalone ECUs connected by a tangle of legacy field buses, we now see zonal controllers aggregating local I/O, centralized compute platforms running safety, mission critical software, and a service-oriented middleware layer stretching across the vehicle.

O-RAN Fronthaul Security using MACsec

With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist in meeting these challenges.

Seize the Ethernet TSN Opportunity

The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.

Frequently asked questions about Single-Protocol PHY IP

What is Quad Serial Gigabit Media Independent Interface (QSGMII)?

Quad Serial Gigabit Media Independent Interface (QSGMII) is a Single-Protocol PHY IP core from Comcores listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP