Vendor: Zixin Microelectronics Technology Co. Ltd. Category: Single-Protocol PHY

PCIe PHY

Full compatible with PIPE4.2 interface specification

SMIC 14nm SF+ View all specifications

Overview

Full compatible with PIPE4.2 interface specification

Key features

  • Support for PCIe3(8.0Gbps),Backward compatible with 2.5Gbps and 5Gbps for PCIe
  • Full compatible with PIPE4.2 interface specification
  • Support 16bit and 32bit parallel data bus
  • Independent channel power down control
  • Supported reference clock input range from 25M to 400M
  • Programmable transmit amplitude and FFE
  • Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Support receiver detection, Beacon signal generation and detection
  • Support Spread Spectrum clock generation(optional) and receiving
  • Embedded Primary & Secondary ESD Protection
  • HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA
  • Silicon Proven in SMIC14SF+/SF++ with 0.8V and 1.8V power supply
  • Area: 0.32mm2 per-lane

Silicon Options

Foundry Node Process Maturity
SMIC 14nm SF+

Specifications

Identity

Part Number
PCIe PHY
Vendor
Zixin Microelectronics Technology Co. Ltd.
Type
Silicon IP

Files

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Provider

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is PCIe PHY?

PCIe PHY is a Single-Protocol PHY IP core from Zixin Microelectronics Technology Co. Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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