What is PCIe PHY?
PCIe PHY is a Single-Protocol PHY IP core from Zixin Microelectronics Technology Co. Ltd. listed on Semi IP Hub. It is listed with support for smic.
Vendor:
Zixin Microelectronics Technology Co. Ltd.
Category:
Single-Protocol PHY
PCIe PHY
Full compatible with PIPE4.2 interface specification
Overview
Full compatible with PIPE4.2 interface specification
Key features
- Support for PCIe3(8.0Gbps)，Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4.2 interface specification
- Support 16bit and 32bit parallel data bus
- Independent channel power down control
- Supported reference clock input range from 25M to 400M
- Programmable transmit amplitude and FFE
- Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss
- Integrated on-die termination resistors and IO Pads/Bumps
- Support receiver detection, Beacon signal generation and detection
- Support Spread Spectrum clock generation(optional) and receiving
- Embedded Primary & Secondary ESD Protection
- HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA
- Silicon Proven in SMIC14SF+/SF++ with 0.8V and 1.8V power supply
- Area: 0.32mm2 per-lane
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 14nm | SF+ | — |
Specifications
Identity
Part Number
PCIe PHY
Vendor
Zixin Microelectronics Technology Co. Ltd.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Frequently asked questions about Single-Protocol PHY IP
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.