SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consum…
- Samsung
- 14nm
- In Production
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consum…
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported.
HDMI transmitter PHY (Physical layer) IP core which is fully amenable with HDMI 1.4/2.0 specification.HDMI transmitter PHY which …
We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to …
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
USB 3.0 femtoPHY in SMIC (28nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
The transmitter is designed to support Single link transmission between Host and Flat Panel Display up to 1080p resolutions, Dual…
Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe …
High speed analog circuits for USB3.0 PHY application 745um*620um
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.
Rail to rail LVDS receiver 1 Gbps
LVDS_RX is LVDS receiver with rail to rail input range.
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the tr…
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 contr…