Interlaken: the ideal high-speed chip-to-chip interface
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Vendor:
Comcores
Category:
Single-Protocol PHY
Universal Serial 10GE Media Independent Interface (USXGMII)
The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
Overview
The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC). Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
There are options to include support for RS-FEC forward error correction (RSFEC), as per IEEE 802.3 Clause 108, and access to control and status registers through an APB interface.
The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a demultiplexed MAC through multiple XGMII (32-bit data, 4-bit control, single clock-edge interfaces). Connection to the SerDes is through a configurable 16, 20, 32, 40, or 64-bit interface.
Key features
Delivering Performance
- SerDes rates of 5.15625Gbps, 10.3125Gbps and 20.625Gbps with data widths of 16, 20, 32, 40, and 64 bits
Highly Configurable
- Multispeed multi-port or single-port USXGMII interface
- Supporting 100Mbps and 1/2.5/5/10Gbps Ethernet data rates
- Clause 37-type auto-negotiation for link status notification
- Scrambled idle test pattern generator and checker
- 64b/66b encoding/decoding
- Optional clock tolerance compensation on receive (RX) path
- Configurable as a 5GBASE-R or 10GBASE-R PCS compliant with IEEE 802.3
- Clauses 49 and 129
- Data scrambling on transmit (TX) path and descrambling on RX path
- Optional RS-FEC (Clause 108)
- Optional APB control status register interface
Easy to use
- ASIC proven
- Lint/CDC optimized
- UVM regression tested with full coverage
- Customizable with easy integration
- Extremely Compact
- Connection to multiple multi Gigabit Ethernet MACs using demultiplexed
- XGMII interfaces
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Block Diagram
Universal Serial 10GE Media Independent Interface (USXGMII) block diagram
What’s Included?
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- IP in SystemVerilog, Source code or Encrypted RTL
- Comprehensive documentation, including User Manual, Release Note and Product Brief
- Simulation Environment, including basic test environment, test cases and test scripts
- Software demo application, Complete Linux system with
- Full integration into Linux
- Netconf for configuration & management
- Software drivers, C code, Linux device driver, FreeRTOS driver
- IEEE 802.1AS software stack, C code
- Demo: Complete example design targeted AMD/Xilinx ZCU102 hardware platform, with other hardware platforms on request
- Access to support system and direct support from Comcores Engineers
- Timing Constraints in Synopsys SDC format (optional)
- Synopsys Lint (optional)
- Synopsys Lint waiver (optional)
Specifications
Identity
Part Number
Universal Serial 10GE Media Independent Interface (USXGMII)
Vendor
Comcores
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Denmark
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Frequently asked questions about Single-Protocol PHY IP
What is Universal Serial 10GE Media Independent Interface (USXGMII)?
Universal Serial 10GE Media Independent Interface (USXGMII) is a Single-Protocol PHY IP core from Comcores listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.