IO pad library IP provides the physical interface between internal core logic and external chip pins. These libraries are critical for signal integrity, ESD robustness, voltage domain interoperability, manufacturability, and reliable chip-level integration across semiconductor products.
Explore IO pad IP libraries including GPIO, analog pads, high-speed pads, and protection structures tailored to foundry process requirements.
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50…
1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
A TSMC 22nm Inline, Flip Chip compatible library with GPIO, ODIO, HDMI, LVDS, & Analog Cells.
Specialed 20V Analog I/O in TSMC 55nm
A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
Multi-Voltage GPIO 5V ODIO and Analog/RF I/Os in TSMC 65nm
1V/3.3V GPIO with I2C ODIO and 3.3V & 5V Analog Cells in TSMC 65nm Key attributes of this IO library include dual independent IO …
1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
High Performance Single-Ended / Differential I/O Macro in TSMC 16FFC This library is a production-quality, silicon-proven I/O Lib…
High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
A 3.3V wirebond I/O library with 8kV HBM ESD protection, a 1.2Gbps LVDS, GPIO, and I2C compliant ODIO in an ultra-small footprint.
Three-Speed Inline Library with Open Drain I/0 in TSMC 22nm
A TSMC 22nm Inline, Flip Chip compatible library with three-speed GPIOs and I2C compliant ODIO.
GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V SLVS Transceiver.
On-chip ESD/EOS/Latch up/EMC protection for high voltage and BCD processes
Design cost reduction Designing ESD protection can be very costly: frequently many test structures are required, analysis needs t…
Robust circuit and interface solutions
PhyStar® robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g.
Differential IO Buffer on TSMC CLN7FF
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
Differential IO Buffer on TSMC CLN16FFC
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
Differential IO Buffer on TSMC CLN12FFC
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
Differential Clock Receiver to CMOS on TSMC CLN2P
The Differential Clock Receiver macro addresses a large portfolio of applications.
CML Differential IO Buffer on TSMC CLN6FF
The CML to HCSL Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible …
Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
Our I/O Library, meticulously crafted to support a wide range of interfaces critical for modern electronic designs.
Differential Buffer, TSMC N5, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express 3.1 includes the vendor’s high-speed, high-performance transceiver to meet today’s appli…