Vendor: UniIC Category: High-Speed

DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm

The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.

TSMC 12nm FFC View all specifications

Overview

The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM.

It supports DDR5&DDR4 interface. The DDR5 DQ data rate can be up to 4800Mb/s, and the DDR4 DQ data rate can be up to 3200Mb/s and CA is SDR mode.

Key features

  • Compatible with JESD79-4B/5B
  • Combined the DDR5 and DDR4 interface
  • Data Rate:
    • DDR5: Up to 4800 Mbps
    • DDR4: Up to 3200 Mbps
  • Support loopback test
  • Support VREFG for internal DQ receiver
  • Support retain the IO output
  • Programmable On Die Termination:
    • DDR5/4: 240/120/80/60/48/40/34 Ω
  • Block cell includes Local Decap
  • Process Node: TSMC 12nm FinFET
  • Operation Temperature: Tj = -40℃ ~ +125℃

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC

Specifications

Identity

Part Number
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
Vendor
UniIC
Type
Silicon IP

Provider

HQ: China

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Frequently asked questions about High-Speed I/O Pad IP

What is DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm?

DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm is a High-Speed IP core from UniIC listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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