Vendor: Sofics Category: ESD Protection

Robust circuit and interface solutions

PhyStar® robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g.

Overview

PhyStar® robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g. to provide antenna clipping or POR), as well as automotive standard PHYs (e.g. a full LIN PHY with integrated ESD, EOS and EMC robustness).

Higher integration

Overall robustness and cost optimization can be driven further by a higher level of solution integration. Sofics’ design team is ready to enhance the functionality of IP blocks with diverse and/or aggressive ESD/EMC/EOS requirements. In one example, a set of I/O’s with increased HBM performance (4 kV HBM) were created. This allowed the customer to focus on their core circuitry, while Sofics designed the pad ring, allowing a shorter design time for the overall product. The I/O library contained digital and several analog I/O’s, including a high voltage pad – with tolerance for high positive and negative voltages (upto +-6V in a 2.5V domain). Also included was the power ESD power protection, busses and filler cells. The fact that Sofics could act as a one-stop-shop by delivering the entire robust pad ring removed much of the integration overhead, and lowered overall costs significantly.

Mask cost reduction

As in all Sofics’ solutions, we strive for a minimal mask set to meet all requirements. In one example, we delivered digital IO’s for 1.8V-3.6V domain using 5V transistors – as was the customers request.

Benefits

  • Fabless companies that integrate Sofics IP in their IC designs have been able to reduce their costs spanning across reduced design cost, reduced mask and manufacturing costs, lower risks and reduced time-to-market. Below are examples how this was achieved.

Specifications

Identity

Part Number
PhyStar
Vendor
Sofics
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Belgium

Learn more about ESD Protection IP core

EOS protection characterization using Long-Pulse TLP

EOS, or Electrical Overstress, is a significant factor in IC reliability. Sometimes, IC interfaces and/or power pads are subjected to voltage/current levels beyond the absolute maximum rating. Sources claim that more than 40% of the field failures in electronic products are related to EOS.

Frequently asked questions about ESD Protection Library IP cores

What is Robust circuit and interface solutions?

Robust circuit and interface solutions is a ESD Protection IP core from Sofics listed on Semi IP Hub.

How should engineers evaluate this ESD Protection?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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