Vendor: Certus Semiconductor Category: GPIO

1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm

High Performance Single-Ended / Differential I/O Macro in TSMC 16FFC This library is a production-quality, silicon-proven I/O Lib…

Overview

High Performance Single-Ended / Differential I/O Macro in TSMC 16FFC

This library is a production-quality, silicon-proven I/O Library in TSMC 16nm technology. The High Performance GPIO is a flip-chip compatible, 1.2V to 1.8V GPIO design, compliant with multiple high-speed Single-Ended and Differential I/O standards. The macro cell comes as a pair of I/Os that can be configured as a differential I/O or two independent single- ended I/Os. The library is capable of tuned output impedance when paired with our calibration I/O that adaptively tunes to an external precision resistor.

 Operating Conditions

Parameter Value
Devices 1.8V Thick and 0.8V Thin Oxides
BEOL 11 Metals
VDDIO 1.2V, 1.5V, and 1.8V
VDD 0.8V
Tj -40C to 125C
ESD +/- 2kV HBM, +/- 500V CDM

 Cell Names

Cell Size Metal Stack
RS_HPIO_DIF_NS Pair of Digital GPIO, 70x75um
RS_HPIO_DIF_EW Pair of Digital GPIO, 70x75um

 Single-Ended Standards

  •  LVCMOS: 2mA, 4mA, 6mA, 8mA, 12mA and 16mA
  •  HSTL: Class 1 & 2
  •  SSTL: Class 1 & 2
  •  HSUL
  •  POD

 Differential Standards

  •  LVDS
  •  DIFF_HSUL
  •  DIFF_POD
  •  SLVS
  •  MIPI

 

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm —

Specifications

Identity

Part Number
RS16
Vendor
Certus Semiconductor
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: United States

Learn more about GPIO IP core

CDM Dependence on Device Capacitance

This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

Field Induced CDM Explained

Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Frequently asked questions about GPIO Pad Library IP cores

What is 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm?

1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm is a GPIO IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP