The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
- Modulation Demodulation
- silicon proven
- immediately
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
The IPrium-SOQPSK-LDPC-Modulator IP Core implements constant amplitude CPM SOQPSK modulation with LDPC Coding.
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
Vision DSP built using 128-bit SIMD and offering up to 0.4 TOPS of performance
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Cache-Coherent HiFi 5s Symmetric Multiprocessor
Efficient 32-bit processing for audio enhancement algorithms, wideband voice codecs, and multi-channel audio The Cadence® Tensili…
Efficiently supports front-end audio processing like beamforming and noise reduction, as well as neural network-assisted speech r…
PUSCH Equalizer for 3GPP 5G NR
3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel sol…
100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm wit…
CCSDS 231.0 LDPC(128, 64) and LDPC(512, 256) Encoder and Decoder
The IPrium-LDPC-CCSDS-231-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm f…
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, …
LDPC corrects errors caused by flash storage failure mechanisms.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specifi…
DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
The is a single-chip DVB-T, T2, C, S and S2 demodulator IP core extratced from production chip and silicon proven IP core.