Reed Solomon FEC

Wide range of dedicated, high performance, low latency RS FEC IP cores to meet any error correction requirement

The Reed Solomon Forward Error Correction (RS FEC) IP is a highly optimized and silicon agnostic implementation of the RS FEC encoder and decoder algorithm targeting both ASICs and FPGAs. The algorithm for RS-FEC is used across multiple standards in the industry as listed in the table below. Our solution is optimized towards each application individually to offer the best performance, size, and lowest latency.

The core enables quick and reliable deployment of both the encoder and the decoder. The symbol size (m) is application specific usually 8 or 10 bits and the error correction capability depends on the parity bits attached to the message (n-k)/2 = t.

The IP can be accommodated to any parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been the key component for all of the IP cores in our portfolio which use RS-FEC encoding.

The RS FEC IP consists of two separate modules, the encoder and decoder, to be instantiated in the TX and RX data paths of the design. These modules include necessary gearboxes for efficient data processing as well as the required Polynomial Dividers. There can be multiple polynomial dividers instantiated in parallel if a design calls for this type of optimization.

The Encoder also uses an additional gearbox to make room for the parity data in the data path, and the message and parity are merged before being output out of the design. The Decoder will perform  the necessary error calculation and correction on the delayed data. Final gearbox is also optionally available where needed to convert from the RS FEC symbol form to the PCS data bus width.

• Designed to support any Reed Solomon code.
• Custom tailored to support specific codes see standard table below
• Low Latency
• FEC Processing cycles optimized for reduced buffering
• Compact Implementation
• Data bus width Variants for Logic Size to Clock Frequency balancing
• Verilog-based (SystemVerilog)

• Test Environment
  • All RSFEC IPs are tested against a VIP model in UVM regression for full functional coverage
• Silicon Agnostic
  • Designed in Verilog and targeting both ASICs and FPGAs
• Silicon Proven
  • Multiple tapeouts as crucial integrated component of Chip Interfaces other IP offerings
• Active Support
  • All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format.
• The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request