DVB-CID (Digital Video Broadcast - Carrier Identification System) is an ETSI standard for interference prevention within digital …
- Modulation Demodulation
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
DVB-CID (Digital Video Broadcast - Carrier Identification System) is an ETSI standard for interference prevention within digital …
Constant False Alarm Rate Processor (CFAR)
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver ass…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
LMS Adaptive Channel Equalizer
The AH1001_LEQ LMS Adaptive Channel Equalizer (LEQ) FPGA core provides a 17-tap Least Mean Squares (LMS) signed-error adaptive Ch…
DVB-RCS (Digital Video Broadcasting – Interaction channel for satellite distribution systems) is an established ETSI standard for…
IEEE 802.11ad (WiGig 60GHz) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard …
MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastic…
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second…
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…
32-bit Floating-point Square-root IP Core
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard.
IEEE 802.11n/ac/ax (WiFi) LDPC Decoder and Encoder
The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs).
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast – Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmissio…
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN).
GEO-Mobile Radio (GMR) LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones.
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.
The BCH decoder has four main functional blocks along with memory blocks.
Compliant with the Telemetry IRIG 106 Standard
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol tim…