In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
- Channel Coding
- Mature
- Now
- DVB-S2
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
Noesis Technologies ntSYNC is a fully programmable component used to achieve time and frequency synchronization in OFDM technolog…
DVB S2/S Satellite Tuner SoC White Box IP
This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting.
The MVD ISDB-T core is a drop-in module that includes the following functions : • Input data framer from DVB-SPI source (MPEG-TS …
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
The DVB-T2 core allows the transmission of an MPEG-TS data stream to a digital to analog converter in base band, IF or RF mode.
2.5 Gb/s Digital RF Up Converter for AD9739A
The MVD Upconverter core is a drop-in module that converts multiple baseband I-Q signals to analog RF signal with AD9739 or AD973…
The LCD01G is a fully compatible GEO Mobile Radio (GMR-1) LDPC error control decoder.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP.
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
The eSi-QRD-LSL is a QR-Decomposition Least Squares Lattice (QRD-LSL) core is a high throughput IP core that finds application in…
A efficient pipelined radix-2 squared FFT.
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.