Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
- Channel Coding
- In Production
- Immediate
- WiMAX, DVB
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizab…
Radar processing IP suite for Advanced Driver Assistance Systems
The eSi-ADAS™ is a suite of radar accelerator IP including a Radar co-processor engine, they enhance the overall performance and …
Kalman Filter hardware accelerator
The eSi-Kalman core provides hardware acceleration for Kalman Filtering (KF) and related target tracking algorithms, such as meas…
High performance FFT optimised for Radar
A configurable efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generati…
Ceva-SensPro is a family of DSP cores architected to combine vision, Radar, and AI processing in a single architecture.
The Ceva-BX1 audio digital signal controller IP handles both modest signal-processing and control workloads with up to 8 GMACs pe…
The IntelliProp IPC-BL119A-ZM is a configurable IP core that provides a method of extending an information block with extra bits …
32-512 Point Streaming FFT Core
The FFT1-32-512/4 core implements 32, 64, 128, 256, and 512 point FFT and IFFT in hardware that runs at the clock frequency four …
DSP Extention Superscalar Processor
D15/D15F are the first dual-issue superscalar AndesCore™ processors.
The K-best decoder is part of the MIMO decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The LTE Lite PHY supplied as a portable and synthesizable Verilog-2001 IP.
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
The K-best decoder is part of the MIMO decoder.
The K-best decoder is part of the MIMO decoder.
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.