The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…
- Controller + PHY + 1
- DDR3
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…
DDR/DDR2 SDRAM Controller MACO Core
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.
DDR SDRAM Controller - Non-Pipelined
This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
Convolutional encoding is a process of adding redundancy to a signal stream.
Color Space Converters (CSC) are used in video and image display systems including televisions, computer monitors, color printers…
CMOS to MIPI CSI-2 Interface Bridge IP
Many traditional image sensors have a CMOS interface.
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.
The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described…
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
The GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA ORT42G5 FPSC and provides the PCS …
The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 …
The 10 Gigabit Ethernet (10 GbE) Physical Coding Sublayer (PCS) solution from Lattice Semiconductor enables creation of system so…
40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
Display Stream Compression (DSC 1.2) Encoder
The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K.
The Beyond SHA-3 is a high-throughput, area-efficient hardware implementation of the SHA-3 cryptographic hashing functions, compl…
H.264 High 10 Intra Profile Encoder
The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…