The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets …
- SPI / QSPI XSPI
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets …
Serial RapidIO 2.1 Endpoint IP Core
The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…
Serial RapidIO - Physical Layer Interface
The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.
Many digital systems use filters to remove noise, provide spectral shaping, or perform signal detection.
The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with …
RGB to MIPI DSI Display Interface Bridge
Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Reed-Solomon codes are used to perform Forward Error Correction.
Quad SPI-3 to SPI-4 PHY Layer Bridge
The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and…
Quad SPI-3 to SPI-4 Link Layer Bridge
The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and…
Lattice's Quad GbE Over SONET/SDH Bridge is a hard IP Core implemented in two Lattice ORCA4E06 devices that act as a bridge betwe…
QDRII + SRAM Controller MACO Core
The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller…
Platform Manager Utility Function Core IP
Platform Management Core IP adds two key power-management functions to Platform Manager: Fault Logging and Enhanced Closed-loop T…
Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) la…
PCI Express x1, x4 Root Complex Lite IP Core
PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…
Many digital systems use filters to remove noise, provide spectral shaping, or perform signal detection.
OpenLDI LVDS to MIPI DSI Display Interface Bridge
Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.
One Input to Two Output MIPI DSI Display Splitter Bridge
Many new applications such as virtual reality, augmented reality, and digital cameras require expansion of the number of display …
One Input to Two Output MIPI CSI-2 Camera Splitter Bridge
Mobile cameras and processors are being used for new and exciting applications.
One Input to One Output MIPI DSI Display Interface Bridge
Mobile processors and displays are being used for new and exciting applications.