Vendor: Logic Design Solutions Category: SATA Controller

SATA Host on Xilinx Zynq Artix 7

The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…

Overview

The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 HOST XA7 IP is compliant with Serial ATA III specification and signaling rate is fixed to 6Gbs. The LDS SATA 3 HOST XA7 IP is fully synchronous with system frequency (Clock_sys) at 75MHz in case of 3Gbs speed selection and 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.

Block Diagram

LDS-SATA2-HOST-XZA7-1 block diagram

Benefits

  • The demo provided makes a Disk Read and Write performance test on each disk connected. A counter value is written on the disk and then read back.
    • SATA 2
    • Transfer Data : 80 Giga Byte data transfer with incompressible data.
    • SAMSUNG 850 PRO 1TB SSD
      • Sequential Write : 250 MBytes/s
      • Sequential Read : 270 MBytes/s

Specifications

Identity

Part Number
LDS-SATA2-HOST-XZA7-1
Vendor
Logic Design Solutions
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about SATA Controller IP core

Frequently asked questions about SATA Controller IP

What is SATA Host on Xilinx Zynq Artix 7?

SATA Host on Xilinx Zynq Artix 7 is a SATA Controller IP core from Logic Design Solutions listed on Semi IP Hub.

How should engineers evaluate this SATA Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SATA Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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