Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
- Hash / MAC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores.
AES-CCM Authenticated Encrypt/Decrypt Engine
The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Programmable Advanced Encryption Standard Engine
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Ultra-Fast Baseline and Extended JPEG Decoder
This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 sta…
Baseline and Extended JPEG Decoder
The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Exten…
This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard.
Ultra-Fast Baseline and Extended JPEG Encoder
This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 s…
Baseline and Extended JPEG Encoder
This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 stand…
This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard.
hellaPHY™ RSTD IP core addresses new FCC E911 indoor location accuracy requirements, and opens the door for low-cost IoT wireless…
Atria Logic Pvt.
ADS-B (ES) receiver offers a comprehensive solution for the reception of flight and traffic information.
ADS-B (UAT) receiver offers a comprehensive solution for the reception of flight, traffic and weather information.
100BASE-T1 (OABR) Ethernet PHY IEEE 802.3bw Compliant
CT25204 is a physical layer for Open Alliance BroadR-Reach® and IEEE 802.3bw Ethernet communication within the car.
The AL-USB2D-CTRL fully synthesizable core implements a high/full-speed (480Mbps/12Mbps) peripheral controller that interfaces to…
DDR-I/II/III CONTROLLER IP CORE
DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targ…
The H.265 HEVC Decoder System IPr is a optimized and parameterisable IP Core targeted exclusively at Intel FPGA technology.