The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm.
- Symmetric Crypto
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm.
The silicon proven USB host controller is compliant with USB 1.1 and OHCI 1.0 Specifications.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
This is a high speed 8 state 3GPP™ (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible paralle…
AXI2CHI · CHI-AXI · CHI-CPI · AXI4-SFI
IO coherency · SLC integration · CHI RN-I
SLC / L3 · 4 MB–32 MB+ · CHI HN-F
Input/Output Memory Management Unit
SMMUv3 · Two-stage translation · DMA protection
Configurable transformer accelerator
For fast, low-power edge AI inference on Stories260K, Stories15M, SmolLM 135M, LLaMA 3.2, and custom models, supporting FP32, INT8, and INT4.
Over-Voltage Lockout (OVLO) IP
Over-Voltage Lockout for protection of battery-operated circuits
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
ML-KEM-X Post-Quantum Cryptography Core
Scalable, Parameterized, ACVP-Validated Key Encapsulation IP for FIPS 203 Compliance
DC-DC Split-Pi Boost-Buck Converter
Cascaded 3.3V boost-buck converter running either on a 10V up to 30V supply or on a backup battery supply
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven, fully featured avionics data bus solution purpose-built for defense, ae…
SmartDV’s UFS (Universal Flash Storage) 5.x Device IP is a next-generation storage interface solution designed for flash memory c…
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
SmartDV’s Ethernet 800G PCS (Physical Coding Sublayer) IP Core is engineered to deliver robust and efficient data encoding, align…
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universa…
SmartDV’s AES ( Encryption Standard) IP core is a silicon-proven, hardware-accelerated encryption solution engineered for SoC app…