Vendor: Small World Communications Category: Channel Coding

3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder

This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.

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Overview

This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder. The decoder can be used to decode the standard 3GPP or 3GPP2 8 state turbo code and 16, 32, 64 or 256 state convolutional codes. The PCD03V offers unparalleled speed, performance, low complexity and features compared to other available 3GPP or 3GPP2 decoder cores.

Key features

  • Turbo Decoder
    • 8 state 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible
    • Rate 1/2, 1/3, 1/4 or 1/5
    • 40 to 5114 (3GPP UMTS), 40 to 6144 (3GPP LTE) or 17 to 21504 (3GPP2) bit interleaver
    • Optional external interleaver parameters for 3GPP LTE and programmable row coefficients for 3GPP2 interleaver
    • Up to 309 MHz internal clock
    • Up to 29.4 Mbit/s with 5 decoder iterations
    • 6-bit signed magnitude input data
    • Optional log-MAP or max-log-MAP constituent decoder algorithms
    • Up to 128 iterations in 1/2 iteration steps
    • Optional power efficient early stopping
    • Optional extrinsic information scaling and limiting
    • Estimated channel error output
    • Implement one, two, three, or four different standards from the one core
    • Free simulation software
  • Viterbi Decoder (Optional)
    • 16, 32, 64 or 256 states (constraint lengths 5, 6, 7 or 9, encoder memory m = 4, 5, 6 or 8)
    • Rate 1/2, 1/3 or 1/4
    • Data lengths from 1 to 32768-m bits with tail termination of m bits
    • Optional tail biting decoding from m to 2048 data bits
    • Up to 7.1 Mbit/s (256 state) or 24.4 Mbit/s (16, 32 or 64 states)
    • 6-bit signed magnitude input data
    • Estimated channel error output
  • Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.

Block Diagram

PCD03V block diagram

What’s Included?

  • All licenses
    • Xilinx VHDL core
    • Test vector generation software
  • VHDL ASIC License
    • ASIC VHDL core
    • C++ bit/cycle exact simulation model

Specifications

Identity

Part Number
PCD03V
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Small World Communications

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Frequently asked questions about Channel Coding IP cores

What is 3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder?

3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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