ML-KEM-X Post-Quantum Cryptography Core

The VIC-ML-KEM-X is a highly efficient, production-ready hardware IP core implementing the ML-KEM Post-Quantum Cryptography (PQC) standard, fully compliant with the definitive NIST FIPS 203 specification.

Featuring a flexible, compile-time parameterized architecture, the core can be configured to support a single dedicated security strength or a dual-mode configuration with dynamic, software-driven runtime selection. The core accelerates the entire post-quantum public-key cryptographic loop—including Key Generation, Encapsulation, and Decapsulation—shielding communications against future quantum-tier threats while optimizing resource allocation for constraint-driven System-on-Chip (SoC) architectures.

Feature Definitive FIPS 203 Compliance

• Implements the finalized NIST ML-KEM standard, eliminating regulatory risk and ensuring long-term cryptographic interoperability.

Scalable Architecture Profiles

• Configurable via pre-synthesis parameters to instantiate dedicated standalone hardware (512-only or 768-only) or a dynamic dual-mode configuration.

100% ACVP Validated

• Proven architectures; successfully passes 100% of the official NIST ACVP internal projection vector suites across all execution paths (KeyGen, Encap, Decap) for both 512 and 768 profiles.

Ultra-Lean Footprint

• Fits inside a compact 12.45k LUT envelope in the baseline configuration, leaving ample programmable logic available for application-layer circuits. Aggressive Timing

Closure Achieves a 6.25 ns

• core clock period target, allowing seamless integration into high-frequency embedded clock domains.

Native Montgomery Domain Processing

• Keeps polynomial coefficients within the Montgomery domain throughout back-to-back lattice arithmetic operations (NTT/INTT), eliminating redundant reduction cycles and maximizing pipeline efficiency.

Minimal DSP Utilization

• Consumes only 6 DSP blocks, meticulously optimized to preserve scarce math tiles on budget-sensitive target FPGAs.

Side-Channel Analysis (SCA) Defense

• Features advanced, localized temporal jitter mitigation within the underlying Keccak (SHA3/SHAKE) processing engines to counter non-invasive physical attacks.

Full Subsystem Monolithic Core

• Combines KeyGen, Encap, and Decap into a single tightly coupled state machine, minimizing integration complexity and processor interaction.

Standardized SoC Interfaces

• Packaged with industry-standard control and data interfaces to optimize bus mapping, processor offloading, and standard DMA controller pairing.