AES IP

SmartDV’s AES (Advanced Encryption Standard) IP core is a silicon-proven, hardware-accelerated encryption solution engineered for SoC applications across mobile, automotive, storage, and high-performance embedded systems. Fully compliant with NIST FIPS 197, it implements the AES Rijndael block cipher algorithm with support for AES-128, AES-192, and AES-256 key lengths, delivering robust, standards-compliant data protection for the most security-sensitive applications.

As data security requirements become increasingly critical across every segment of the semiconductor market, having a proven, flexible AES implementation is no longer optional. SmartDV’s silicon-proven AES IP gives SoC teams a production-tested encryption core that supports a comprehensive range of cipher modes — from storage-focused XTS and LRW to authenticated encryption with GCM and CCM — eliminating the risk and complexity of building cryptographic IP from scratch.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, user-programmable key size, and optional key expansion support enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

Compliance and Compatibility

• Fully compliant with NIST FIPS 197 (AES) — updated May 2023
• Optional support for NIST SP 800-38 series including SP 800-38A (ECB, CBC, CFB, OFB, CTR), SP 800-38C (CCM), SP 800-38D (GCM), and SP 800-38E (XTS)
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Secure and Flexible Encryption – Supports AES-128, AES-192, and AES-256 key sizes for scalable security based on application needs
• Versatile Cipher Mode Support – Enables ECB, CBC, OFB, CFB, GCM, CCM, XTS, LRW, and CTR for a wide range of encryption use cases
• Efficient and High-Performance Design – Delivers low-latency, high-throughput encryption and decryption ideal for performance-sensitive systems
• Customizable Key Handling – Works with pre-expanded keys or integrates optional key expansion for flexible integration into system designs
• Advanced Data Handling – Supports block padding, authentication tag appending, and tag verification for complete AES workflow support