SMMUv3 · Two-stage translation · DMA protection
Input/Output Memory Management Unit providing address translation, memory protection, and DMA access control for peripheral devices on the NoC.
Key specifications
| Spec | SMMUv3 |
| Translation | Two-stage S1+S2 |
| TLB | Hardware walker |
| Interface | CHI slave port |
| Interrupts | Fault reporting |
| Deployment | Compute silicon |
Technical details
| Translation stages | S1 and S2 |
| Page sizes | 4KB 16KB 64KB 1GB |
| TLB entries | Configurable |
| NoC attach | CHI RN-I |
| OS support | Linux SMMU driver |
| Silicon | Compute silicon |
Input/Output Memory Management Unit is a System Controller IP core from Signature IP Corporation listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.