Adaptive Voltage Scaling (AVS) Bus Target IP
Provides full AVS Bus slave functionality compliant with the AVS Bus specification.
- Power Management Controller
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Adaptive Voltage Scaling (AVS) Bus Target IP
Provides full AVS Bus slave functionality compliant with the AVS Bus specification.
Adaptive Voltage Scaling (AVS) Bus Host Controller
Designed to enable efficient, high-speed communication between the SoC processor subsystem and external voltage regulators through the industry-standard AVS Bus protocol.
Multi-Protocol AMBA Support - Advanced Routing & Arbitration - Virtual Channel Deadlock Avoidance - Unlimited Scaling
XTAL oscillator family available in TSMC : 7, 12, 28, 65, 130nm
The V-by-One VIP is fully compliant with the V-by-One standard. Supports THine V-by-One HS, HS Plus
Ultra-low jitter, high SFDR LC-based PLL-12.5GHz
Ultra-low jitter, high SFDR LC-based PLL-12.5GHz for SerDes
Resolution: up to 16Kx16K, RGB/YUV (8-bit), Distortion correction (any-shape transform), scaling, rotation
Resolution: up to 8Kx8K, RGB/YUV (8-bit), Distortion correction (any-shape transform), scaling, rotation, Filter: Bilinear,
The AXI-BRG enables communication between an AXI5 interface and an AXI4 interface.
AXI5-Stream to/from AXI4-Stream Bridges
The AXIS-BRG enables communication between an AXI5-Stream interface and an AXI4-Stream interface.
The APB-BRG enables communication between an APB5 Requester and an APB4 Completer.
The UALink IP supports 800Gbps and 400Gbps bandwidth modes with backward compatibility for 200Gbps and 100Gbps.
General Purpose Low-Dropout (LDO) - TSMC
Voltage regulator with capacitor (LDO) available in TSMC 7, 12, 22, 28, 65, 130nm
High-Performance AXI to UCIe FDI Interface IP for Scalable System Integration
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
Simplified Integration USB PD Capable Type-C Sink IP
Easy to integrate and configure Type-C sink port with Power Delivery. Delivered as RTL and an Analog Front End hard macro.
16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem
Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development
High speed MACsec Engine 100G/200G/400G/800G/1.6T
IEEE 802.1AE-2018 Line-Rate Ethernet Layer 2 Security IP Core