Adaptive Voltage Scaling (AVS) Bus Host Controller

The MAXVY's AVS Bus Host Controller IP is a highly configurable solution designed to enable efficient, high-speed communication between the SoC processor subsystem and external voltage regulators through the industry-standard AVS Bus protocol. Fully compliant with the AVS Bus specification, the IP plays a critical role in Dynamic Voltage and Frequency Scaling (DVFS) applications, allowing software-controlled voltage adjustments to optimize power consumption and system performance in real time.

The controller integrates a flexible Processor Interface that enables seamless communication with the SoC. It supports multiple industry-standard bus protocols, including AXI4-Lite, APB, AHB-Lite, and Wishbone (WSB), providing easy register access for configuration, control, status monitoring, and interrupt handling.

The MAXVY's AVS Bus Controller IP incorporates a comprehensive set of functional blocks to efficiently manage AVS Bus transactions. A dedicated Synchronization Module ensures safe clock-domain crossing between the processor interface and AVS Bus domains, while a programmable Clock Generator produces the AVS Bus clock required for protocol-compliant communication with the target voltage regulator.

A configurable Frame Generator constructs AVS Bus command frames based on software requests, and the Response Decoder processes acknowledgments, status information, and responses received from the AVS Bus target device. An integrated CRC Engine provides cyclic redundancy check generation and verification to ensure reliable communication and robust error detection, enabling secure and efficient processor-controlled voltage management.

The architecture supports voltage programming, status monitoring, fault reporting, and protocol error handling, making it well-suited for advanced power management applications that require fast and reliable regulator control.

• Fully Compliant with AVS Bus protocol specification
• Processor Interface supporting AXI4-Lite, APB, AHB-Lite, Wishbone (WSB)
• Register-based configuration and control interface
• Supports both 2-wire and 3-wire AVS Bus communication modes
• Dedicated Synchronization Module for clock-domain crossing
• Programmable AVS Bus Clock Generator
• AVS Bus Frame Generator for command transmission
• Response Decoder for target status and acknowledgment processing
• Integrated CRC generation and verification engine
• Support for Dynamic Voltage and Frequency Scaling (DVFS)
• Configurable operating parameters for application-specific requirements

• Dynamic Voltage and Frequency Scaling (DVFS)
• Adaptive Voltage Scaling (AVS)
• Processor Core Voltage Management
• Power Optimization and Energy Efficiency
• Thermal Management
• Real-Time Voltage Regulation
• Intelligent Power Delivery Control

• Verilog Source code
• User Guide
• IP Integration Guide
• Simulation Script
• Synthesis Script
• Encrypted UVM Verification Environment
• Basic Testsuite
• Firmware code