High speed MACsec Engine 100G/200G/400G/800G/1.6T

The Chip Interfaces high speed MACsec Engine delivers IEEE 802.1AE-2018 compliant port authentication, data confidentiality and data integrity at full line rate from 100G through 1.6T. It protects components in high speed Ethernet networks used in cloud, datacenter, and backhaul infrastructure. The IP core implements a scalable n-bit pipeline architecture using parallel AES-GCM pipelines with placement above or below the MAC. All four standard complaint cipher suites are supported including XPN, enabling compliance with IEEE 802.1AE.

Security & compliance

• IEEE Std 802.1AE-2018 full compliance
• AES-GCM-128 and AES-GCM-256 cipher suites
• AES-GCM-XPN-128 and AES-GCM-XPN-256
• VLAN-in-Clear (802.1Q tag in plaintext)
• Confidentiality offset — configurable per SA
• Controlled/Uncontrolled port with bypass policy
• Encryption + integrity or integrity-only mode

Performance

• Line-rate encryption & decryption — 100G to 1.6T
• Scalable n-bit parallel pipeline architecture
• Above or below MAC placement
• 128-bit to 4K-bit configurable data bus width
• AXI-Stream and xGMII data interfaces
• Backpressure output with drop flag on Tuser sideband
• Store & forward latency characterized per speed grade

Traffic management

• Multiple SecYs in single IP instance
• Configurable Connectivity Associations per port
• Frame classification by MAC address, VLAN, EtherType
• Per-SecY traffic mapping rules
• Configurable Rx channels per CA/peers
• 4 Security Associations per Secure Channel

Integration & EDA

• AXI4-Lite, APB & AVALON management interfaces
• IEEE 802.1X MKA via wpa_supplicant integration tool
• Linux kernel driver included
• Synopsys SDC timing constraints
• SGDC, Lint, CDC waivers included
• IEEE 802.1AE-conformant configuration register map

Test Environment

• High speed MACsec Engine 100G-1.6T IP is Tested  in UVM regression for functional coverage

Silicon Agnostic

• Designed in Verilog and targeting both ASICs and FPGAs

PHY Integration

• PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment

Active Support

• All support is actively provided by engineers directly

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual, Release Note and Quick Start Guide.
• Simulation Environment, including Simple Testbed, Test case, Test Script.
• Timing Constraints in Synopsys SDC format.
• Access to support system and direct support from Chip Interfaces Engineers.
• Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request