Vendor: Chip Interfaces ApS Category: High-Speed

High speed MACsec Engine 100G/200G/400G/800G/1.6T

IEEE 802.1AE-2018 Line-Rate Ethernet Layer 2 Security IP Core

Overview

The Chip Interfaces high speed MACsec Engine delivers IEEE 802.1AE-2018 compliant port authentication, data confidentiality and data integrity at full line rate from 100G through 1.6T. It protects components in high speed Ethernet networks used in cloud, datacenter, and backhaul infrastructure. The IP core implements a scalable n-bit pipeline architecture using parallel AES-GCM pipelines with placement above or below the MAC. All four standard complaint cipher suites are supported including XPN, enabling compliance with IEEE 802.1AE.

Key features

Security & compliance

  • IEEE Std 802.1AE-2018 full compliance
  • AES-GCM-128 and AES-GCM-256 cipher suites
  • AES-GCM-XPN-128 and AES-GCM-XPN-256
  • VLAN-in-Clear (802.1Q tag in plaintext)
  • Confidentiality offset — configurable per SA
  • Controlled/Uncontrolled port with bypass policy
  • Encryption + integrity or integrity-only mode

Performance

  • Line-rate encryption & decryption — 100G to 1.6T
  • Scalable n-bit parallel pipeline architecture
  • Above or below MAC placement
  • 128-bit to 4K-bit configurable data bus width
  • AXI-Stream and xGMII data interfaces
  • Backpressure output with drop flag on Tuser sideband
  • Store & forward latency characterized per speed grade

Traffic management

  • Multiple SecYs in single IP instance
  • Configurable Connectivity Associations per port
  • Frame classification by MAC address, VLAN, EtherType
  • Per-SecY traffic mapping rules
  • Configurable Rx channels per CA/peers
  • 4 Security Associations per Secure Channel

Integration & EDA

  • AXI4-Lite, APB & AVALON management interfaces
  • IEEE 802.1X MKA via wpa_supplicant integration tool
  • Linux kernel driver included
  • Synopsys SDC timing constraints
  • SGDC, Lint, CDC waivers included
  • IEEE 802.1AE-conformant configuration register map

Block Diagram

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Benefits

Test Environment

  • High speed MACsec Engine 100G-1.6T IP is Tested  in UVM regression for functional coverage

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

PHY Integration

  • PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment

Active Support

  • All support is actively provided by engineers directly

What’s Included?

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request

Specifications

Identity

Part Number
High speed MACsec Engine 100G-1.6T
Vendor
Chip Interfaces ApS
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Chip Interfaces ApS
HQ: Denmark

Learn more about High-Speed IP core

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The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Why What Where DIFI and the new version 1.3

This article will introduce the main concepts of the Digital Intermediate Frequency Interoperability (DIFI) standard including the new features introduced in version 1.3.  With no assumptions of prior knowledge from the reader this should serve as an introduction to the standard but also for those familiar with DIFI raise awareness of the added features of link establishment in new standard version.

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Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about High-Speed I/O Pad IP

What is High speed MACsec Engine 100G/200G/400G/800G/1.6T?

High speed MACsec Engine 100G/200G/400G/800G/1.6T is a High-Speed IP core from Chip Interfaces ApS listed on Semi IP Hub.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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