NoC Interconnect IP Generator

IDS-NoC™ is a scalable Network-on-Chip (NoC) interconnect IP generation solution for modern heterogeneous multi-core SoCs. Built on a packet-switched, distributed architecture, IDS-NoC enables engineering teams to rapidly create, configure, and integrate high-performance interconnect fabrics while eliminating the scalability, timing, and integration limitations of traditional crossbar-based designs. The solution is compatible with Arm® and RISC-V® processor-based systems and supports the development of complex, data-intensive SoCs.

Whether designing an AI accelerator, automotive SoC, multi-core platform, or edge computing device, IDS-NoC provides the scalability, predictability, and automation you need to ship complex SoCs faster.

Protocol

• Multi-Protocol Bus Support: AMBA- AXI4, AHB4, APB, AXI5, ACE

Fabric

• Mesh Topology: N×M mesh with N/S/E/W/Local port routing; linear area scaling, simplified timing closure
• Virtual Channel Architecture: 4 independent VCs (AW/W, B, AR, R); structural deadlock elimination; full QoS configurability
• Network Interface (NI): packetizer AXI <-> FLIT, depacketizer FLIT <-> AXI; Ingress & Egress NI per endpoint
• Pipelined Router Architecture: Input Buffers (FIFO), Routing Computation (RC), Virtual Channel Allocator (VCA), Switch Allocator (SA), Crossbar, Output Buffers (FIFO)
• Memory Re-order Buffer: Optimizes memory transaction ordering to improve bandwidth utilization and overall system performance.

Scale

• Wide Data Bus: Up to 2048-bit data bus width
• Transaction Depth: Up to 1024 pending transactions supported
• Unlimited Scaling: Unlimited NoC instances per design; unlimited Network Interface Units (NIs) per die

Delivery

• Parameterization: Generation-time, elaboration-time, and run-time configurability
• Optimizations: Power management, security, address & data protection, advanced in-circuit debug
• Functional Safety & Reliability: Reliability option, Functional Safety
• RTL Delivery: SystemVerilog, plain-text, unencrypted — full visibility and portability
• Licensing: Flexible licensing model suited for small-scale to large-scale SoCs
• Ecosystem Integration: Deep integration with IDesignSpec for register maps, connectivity, and bus IPs

Faster Time-to-Market

Parameter-driven generation eliminates manual implementation of routers, network interfaces, and interconnect fabrics, allowing teams to rapidly create and iterate on NoC architectures.

Unlimited Scalability

Deploy as many NoC instances and Network Interface Units (NIUs) as required by your design.

Open and Portable RTL

Receive plain-text, unencrypted SystemVerilog RTL with full visibility and auditability.

Deadlock-Free Communication

Dedicated virtual channels and configurable arbitration simplify protocol management and improve reliability.

End-to-End Automation

Integrated with the IDesignSpec Suite for RTL generation, integration, verification, documentation, and sign-off collateral generation.

• AI Accelerators: High-bandwidth, low-latency interconnect for neural processing units and ML inference engines
• Multi-Core Processors: Scalable communication between CPU clusters, caches, and memory controllers
• Edge Computing: Compact, power-efficient NoC for embedded AI and edge inference SoCs
• Aerospace & Defence: Reliable, certified interconnect fabric for mission-critical and safety-qualified designs
• Automotive SoCs / ADAS: ISO 26262-ready interconnect fabric for safety-critical autonomous driving platforms
• Networking & Comms SoCs: High-throughput packet routing for 5G, networking, and protocol processing chips
• Data Center Accelerators: Scalable interconnect for cloud AI chips and custom ASIC accelerators
• Industrial & Consumer Electronics: Flexible NoC for diverse SoC architectures across industrial IoT and consumer devices