AXI5-Stream to/from AXI4-Stream Bridges
The AXIS-BRG enables communication between an AXI5-Stream interface and an AXI4-Stream interface.
Overview
The AXIS-BRG enables communication between an AXI5-Stream interface and an AXI4-Stream interface. The core is designed for minimal latency and area, with its main functions including calculation of check signals from the AXI4-Stream interface and parity checking of signals sent by the AXI5-Stream interface.
The bridge also adds TWAKEUP input/output and offers configuration options to suit different applications. The core provides different error handling options for each signal, including the option to either terminate or propagate the transmission upon error detection.
The AXIS-BRG implements a set of maskable interrupt lines for each AXI-Stream parity signal independently.
The core includes two bridges: a 4-to-5 bridge that connects an AXI4-Stream Transmitter with an AXI5-Stream Receiver, and a 5-to-4 bridge that connects an AXI5-Stream Transmitter with an AXI4-Stream Receiver.
Key features
- Calculation of parity check signals to be sent to the AXI5-Stream interface.
- Parity checking for check signals sent from the AXI5-Stream interface.
- Addition of TWAKEUP signal input/output.
- Registered signals on the AXI5-Stream interface.
- Bus width options:
- 2N data bits, where 2 < N < 11.
- Configurable number of user bits.
- Parity error output line per AXI-Stream signal.
- Configurable error behavior per AXI-Stream signal through mode input:
- Terminate transfer and disable core.
- Continue transfer after error reporting.
- Maskable interrupt lines for parity errors per AXI-Stream signal.
Block Diagram
Applications
The AXIS-BRG is used when two AXI-Stream interfaces of different versions need to communicate.
What’s Included?
Deliverables
The core is available in synthesizable HDL (Verilog) and includes everything required for successful implementation. Its deliverables include:
- Complete test environment.
- Simulation and synthesis script.
- Comprehensive user documentation.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Protocol Bridge IP core
8051s in Modern Systems: Interfacing to AMBA Buses
Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
AMBA AXI Exclusive Access De-mystified
Debug of AMBA AXI Outstanding Transactions
Frequently asked questions about Protocol Bridge IP cores
What is AXI5-Stream to/from AXI4-Stream Bridges?
AXI5-Stream to/from AXI4-Stream Bridges is a Protocol Bridge IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.