APB5 to APB4 bridge

The APB-BRG enables communication between an APB5 Requester and an APB4 Completer. The core is designed for minimal latency and area, with its main functions including calculation of check signals from the APB4 interface and parity checking of signals sent by the APB5 interface.

The bridge also adds PWAKEUP, PNSE, and PUSER outputs to the Completer and offers configuration options to suit different applications. Error handling behavior is programmable for each APB signal independently, including the option to either terminate or propagate the transmission upon detection of an error on each parity signal.

The APB-BRG also implements a set of maskable interrupt lines for each APB parity signal independently.

• Calculation of Requester parity signals.
• Parity checking for Completer parity signals.
• Minimal latency: 3 clock cycles between Completer and Requester.
• Addition of PWAKEUP, PNSE, and PUSER signals as passthrough.
• Registered signals on the APB5 interface.
• Bus width options:
  • 2^N data bits, where 2 < N < 11.
  • 1 to 32 address bits.
  • Configurable number of user bits.
• Parity error output line per APB signal.
• Configurable error behavior per APB signal through mode input:
  • Terminate transfer and disable core.
  • Continue transfer after error reporting.
• Maskable interrupt lines for parity errors per APB signal.

The APB-BRG is used when two APB interfaces of different versions need to communicate, specifically an APB5 Requester and an APB4 Completer.

Deliverables

The core is available in synthesizable HDL (Verilog) and includes everything required for successful implementation. Its deliverables include:

• Complete test environment.
• Simulation and synthesis script.
• Comprehensive user documentation.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.