UALink PHY + Controller

INNOSILICON™ introduces its UALink PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully compliant with UALink Common Specification Rev2.0 standards.

The UALink IP integrates high-performance interconnect 112G/224G SerDes. Fine-grained configuration and strong adaptability deliver stable link transmission in scale-up network and power efficiency under variable traffic, temperature and voltage conditions, satisfying strict long-term silicon operating requirements.

The UALink IP supports 800Gbps and 400Gbps bandwidth modes with backward compatibility for 200Gbps and 100Gbps. It serves as an ideal interconnect solution for devices demanding ultra-high bandwidth, ultra-low latency and super-node architectures. Typical application scenarios include large-scale AI training, HPC, edge-side AI inference, and switching devices.

Leveraging the synergy of “core IP + complete solution”, INNOSILICON™ UALink one-stop IP solution supports advanced cutting-edge process nodes, helping customers mitigate the technical risks of developing UALink interconnect IP. It shortens integration cycles for high-speed inter-chip interfaces in high-performance computing chips and empowers customers to gain a competitive edge in next-generation ultra-low-latency high-bandwidth interconnection solutions.

UALink-Specific Features

• 112G/224G Serdes.
• Supports total  800 or 400Gbps，compliant with 200Gbps or 100Gbps.
• Supports AXI3/4/5 interface or UPLI interface.
• Supports transmission in Ultra low latency mode or High reliability mode.
• Auto-negotiation and link training support for seamless system integration
• Supports channel loss up to 35 dB.
• Supports three RSFEC modes: Bypass FEC/RSFEC-68/RSFEC-272/RSFEC-544.
• Supports In-Network Compute.

UALink Common Features

• Supports MMU in Cluster communication mode ,which is used for AXI address to UPLI port mapping.
• Supports address compression and decompression to improve bandwidth utilization. 
• Supports DL layer Link Level Retransmission mechanism.
• Supports RAS：TX/RX drop mode & isolation mode ,which are meet for automatic AXI error response in the event of a fail within a switch fabric, preventing bus hang.
• Supports Basic/Control/UART message transmission management.
• Supports BIST and AXI performance monitor.
• Supports link control and Tx pacing functions.

• Adopting a multi-dimensional parameter configurable version architecture, it supports three operation modes: Direct Connect, Cluster, and Direct & Cluster Combo. It is compatible with various complex service scenarios such as Mesh topologies and switching fabrics to meet diverse deployment requirements.
• AI Era-ready performance: higher data rates, lower power consumption, smaller area, and robust link reliability.
• Flexible harden IP delivery options to accelerate integration and reduce customer costs.
• Advanced packaging and PCB co-design to fully unlock IP performance and stability.
• Comprehensive support from design through mass-production bring-up, ensuring worry-free and timely service quality.

• Databook, integration guide, and other related documentation
• Simulation models and test cases
• LIB, LEF
• Standardized software drivers
• SI/PI analysis reports
• Sign-off reports
• GDSII