UALink PHY + Controller

INNOSILICON unveils its UALink PHY and Controller IP, engineered specifically to meet the AI era’s demanding high-performance SoC requirements. The solution delivers full compliance with the UALink Common Specification Rev 2.0, ensuring seamless interoperability and next-generation scale-up.

UALink IP integrates 112G/224G SerDes to deliver stable, scalable, and power-efficient link performance. Fine-grained configuration and strong adaptability ensure reliable operation across varying traffic, temperature, and voltage conditions, meeting long-term silicon reliability requirements.

UALink IP supports 800G and 400G bandwidth modes with backward compatibility to 200G and 100G, making it an ideal interconnect for ultra-high bandwidth, ultra-low latency, and super-node architectures. It is well suited for large-scale AI training, HPC, edge AI inference, and switching devices.

UALink-Specific Features

• 112G/224G Serdes.
• Supports total 800 or 400Gbps，compliant with 200Gbps or 100Gbps.
• Supports AXI3/4/5 interface or UPLI interface.
• Supports transmission in Ultra low latency mode or High reliability mode.
• Auto-negotiation and link training support for seamless system integration
• Supports channel loss up to 35 dB.
• Supports three RSFEC modes: Bypass FEC/RSFEC-68/RSFEC-272/RSFEC-544.
• Supports In-Network Compute.

UALink Common Features

• Supports MMU in Cluster communication mode ,which is used for AXI address to UPLI port mapping.
• Supports address compression and decompression to improve bandwidth utilization.
• Supports DL layer Link Level Retransmission mechanism.
• Supports RAS：TX/RX drop mode & isolation mode ,which are meet for automatic AXI error response in the event of a fail within a switch fabric, preventing bus hang.
• Supports Basic/Control/UART message transmission management.
• Supports BIST and AXI performance monitor.
• Supports link control and Tx pacing functions.

• UALink uses a multi-dimensional, configurable architecture supporting Direct Connect, Cluster, and Combo modes. It fits complex deployments like Mesh topologies and switching fabrics for flexible system integration.Flexible harden IP delivery options to accelerate integration and reduce customer costs.
• Advanced packaging and PCB co-design to fully unlock IP performance and stability.
• Comprehensive support from design through mass-production bring-up, ensuring worry-free and timely service quality.

• Databook, integration guide, and other related documentation
• Simulation models and test cases
• LIB, LEF
• Standardized software drivers
• SI/PI analysis reports
• Sign-off reports
• GDSII
• RTL Model
• Drivers