Ultra-low jitter, high SFDR LC-based PLL-12.5GHz

An LC-oscillator-based charge-pump PLL that provides ultra-low jitter (250 fs RMS jitter in 1kHz-100MHz of integration bandwidth) and high SFDR (60dBc at the reference frequency of 62.5MHz). Its ultra-low jitter makes it suitable for JESD204C-B12-compliant high-speed interface architecture. It features a programmable divider and a wide tuning range, enabling support for multiple coding schemes and operating frequencies in a JESD204C-B12 standard-compliant high-speed interface

• Ultra-low jitter, 250fs rms jitter at 12.5GHz, designed to support JESD204C-B12 compliant high-speed interface architectures.
• The generated output frequency can vary from 10GHz to 12.5GHz with an input frequency of 62.5MHz.
• Programmable integer divider.
• Output frequency step of 62.5MHz.
• Locking time of 10µs.
• 4 multi-phase clocks are obtained simultaneously.

• Ultra-low jitter (250fs rms jitter at 12.5GHz)
• Reduces jitter-induced degradation of eye opening, timing margin, and link robustness
• High SFDR (60dBc at 12.5GHz)
• Reduces deterministic clock-related impairments that can degrade SERDES performance
• Wide tuning range (from 10GHz to 12.5GHz)
• Enables flexible support of different SERDES lane rates and configurations
• Integer-N multiplication with reference frequency of 62.5MHz
• Low power consumption: 25mW
• Highly compact and easy to integrate

• JESD204C-B12 standard complaint high-speed interface
• ADC and DAC sampling clock generation for high resolution/dynamic range

• GDSII layout
• Integration support
• DRC, LVS reports
• Verilog (or SystemVerilog) behavioral model
• Datasheet with characterization results
• Timing View (Liberty)
• CDL netlist for LVS
• LEF abstract
• Verification report