DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
- PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY
The DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface.
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface.
VBO Receiver with four and eight lanes for video communication
VBO Transmitter with 8 lanes and 16 lanes for video communication
UCIe Controller (CHI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
UCIe Controller (AXI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
Die-to-Die (D2D) Interface for Chiplet Application
Compliant with the UCIe Specification Revision 1.1
300µA Voltage Buffer - X-FAB XT018
300 μA Unity Gain Buffer with 5.5 MHz Gain Bandwidth
6mA Voltage Buffer - X-FAB XT018
6 mA Unity Gain Buffer with 6.5 MHz Gain Bandwidth
32-bit RISC multiprocessor platform for the most demanding computational tasks
30V 0.5A Hysteretic Buck LED Driver
30V 0.5A Hysteretic Buck LED Driver with High-Side and Low-Side Current Sensing on X-FAB XT018-0.18µm BCD-on-SOI CMOS
Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
The TS_TEMP_DET_X8 is a hysteresis detector that asserts output OVERTJ once junction temperature exceeds 147.2°C and subsequently…
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
VisionNet v1.0 is a configurable CNN accelerator IP designed to deliver efficient edge inference for vision workloads.
RISC-V Display Connectivity Subsystem (DCS)
Modern display links have evolved into complex communication systems requiring continuous management of authentication, topology,…
250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
The TS_IREF_88uA_X8 is a current reference biasing circuit which provides a sink/source ZTAT (zero-toabsolute temperature) temper…
UCIe D2D Adapter & PHY Integrated IP
A UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…
Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.