Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.
- JPEG
- Decoder
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
TMC’s frame rate converter uses an original frame interpolation technology and creates highly accurate interpolation frames with compact circuit resources.
H.264/AVC 1080 60p Baseline Profile Decoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)
H.264/AVC 1080 60p Baseline Profile Encoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
A two-stage secure boot that extends trust from the protected FPGA configuration to the application firmware.
The memory subsystem of the new generation of AI chips needs to have numerous features, such as the ability to reduce latency, co…
AXI2CHI · CHI-AXI · CHI-CPI · AXI4-SFI
IO coherency · SLC integration · CHI RN-I
SLC / L3 · 4 MB–32 MB+ · CHI HN-F
Input/Output Memory Management Unit
SMMUv3 · Two-stage translation · DMA protection
Configurable transformer accelerator
For fast, low-power edge AI inference on Stories260K, Stories15M, SmolLM 135M, LLaMA 3.2, and custom models, supporting FP32, INT8, and INT4.
Over-Voltage Lockout (OVLO) IP
Over-Voltage Lockout for protection of battery-operated circuits
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
ML-KEM-X Post-Quantum Cryptography Core
Scalable, Parameterized, ACVP-Validated Key Encapsulation IP for FIPS 203 Compliance
DC-DC Split-Pi Boost-Buck Converter
Cascaded 3.3V boost-buck converter running either on a 10V up to 30V supply or on a backup battery supply
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven, fully featured avionics data bus solution purpose-built for defense, ae…
SmartDV’s UFS (Universal Flash Storage) 5.x Device IP is a next-generation storage interface solution designed for flash memory c…