Overview
The memory subsystem of the new generation of AI chips needs to have numerous features, such as the ability to reduce latency, consume less energy, provide higher bandwidth, support more DRAM protocols, and reserve channels for newer DRAM technologies, thereby extending product cycles, increasing application coverage, and improving product market competitiveness. OPENEDGES Memory Subsystem has been rapidly designed and engineered to incorporate it into SoCs for various AI markets.
OPENEDGES Memory Subsystem provides ActiveQoS advanced traffic control. As part of ActiveQoS, OIC, and OMC prioritize traffic based on urgency and the manager's property to deliver latency-sensitive traffic on time. ActiveQoS uses the buffer status from the OMC and subordinate monitor IPs to manage traffic from the manager. ActiveQoS reduces latency and bandwidth in OIC by interacting with the memory controller. As a result, ActiveQoS allows OIC to maintain steady traffic while avoiding blocking and congestion caused by overcrowding.
Learn more about DDR IP core
This solution brief highlights how Samsung’s mainstream 8nm process node and LPDDR5X (LP5X) memory together deliver an optimized balance of performance, bandwidth, power efficiency, and cost. The combination enables scalable AI inference across diverse computing environments, from edge devices and AI appliances to emerging inference-focused AI infrastructure, making advanced AI deployment more accessible for startups, fabless innovators, and OEMs alike.
Brett Murdock, Dana Neustadter (Synopsys)
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
