Mesochronous Bridge for PCIe/CXL
Timing-Agnostic PCIe/CXL Bridge for Prototyping & Emulation
- PCI Express
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Mesochronous Bridge for PCIe/CXL
Timing-Agnostic PCIe/CXL Bridge for Prototyping & Emulation
Desktop-class graphics within a mobile power budget
Fully compliant with OpenGMSL v3.0
Fully compliant with OpenGMSL v3.0 specification (March 2026)
Switched Capacitor 3.6V Boost-Buck DC-DC Converter
DC-DC Switched Capacitor Boost-Buck Converter IP in X-FAB XC018-0.18µm CMOS
Cloud and Data Center Compute Subsystem
Fast, scalable, and flexible Arm Neoverse CSS N4 is the most configurable Neoverse compute subsystem, with flexible options for CPU cores, cache sizing, memory, and I/O.
Protocol-Neutral Custom Fabric
Flexible, software-defined fabric IP for custom protocols, AI workloads, and chiplet-scale systems.
Configurable Cache Coherent Fabric IP
Scalable Coherent Connectivity for Advanced SoCs and Chiplet Systems
Configurable AMBA Non-Coherent Fabric IP
Flexible, High-Performance Connectivity for SoCs and Chiplet Systems Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficientl…
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
Compliant to NIST FIPS PUB 197
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
TMC’s frame rate converter uses an original frame interpolation technology and creates highly accurate interpolation frames with compact circuit resources.
H.264/AVC 1080 60p Baseline Profile Decoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)
H.264/AVC 1080 60p Baseline Profile Encoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
A two-stage secure boot that extends trust from the protected FPGA configuration to the application firmware.
The memory subsystem of the new generation of AI chips needs to have numerous features, such as the ability to reduce latency, co…